Soft-start voltage circuit

ABSTRACT

A soft-start voltage circuit includes an operational amplifier, a first and a second capacitors, a first and a second switches, and a voltage level shifter. The operational amplifier includes a positive end, a negative end, and an output end coupled to the negative end of the operational amplifier for outputting the soft-start voltage. The voltage level shifter is coupled between the first capacitor and the positive end of the operational amplifier for shifting a level of the voltage on the first capacitor. The first switch is coupled between the first and the second capacitors for coupling the first and the second capacitors according to the clock. The second switch is coupled between the second capacitor and the negative end of the operational amplifier for coupling the second capacitor and the negative end of the operational amplifier according to the inverted clock.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a soft-start voltage circuit, and moreparticularly, to a soft-start voltage circuit for providing a soft-startvoltage to a DC/DC converter.

2. Description of the Prior Art

Please refer to FIG. 1. FIG. 1 is a diagram illustrating an erroramplifier EA in a DC/DC converter. The error amplifier EA is utilized tocompare a feedback voltage V_(FB) from an output voltage VOUT of theDC/DC converter with a reference voltage V_(REF) or a soft-start voltageV_(SOFT) for generating an error signal S_(ERROR) to adjust the level ofthe output voltage V_(OUT) of the DC/DC converter as desired.

Generally speaking, at the start phase of a DC/DC converter, the outputvoltage V_(OUT) of the DC/DC converter is still at a very low level. Asa result, if the error amplifier EA compares the feedback voltage V_(FB)from the output voltage V_(OUT) with the reference voltage V_(REF) atthe time, the gain of the error signal S_(ERROR) generated by the erroramplifier EA is relatively high. In such condition, the DC/DC convertergenerates a current with a very large magnitude, which is so calledinrush current, for raising the output voltage V_(OUT) to the requiredvoltage level. In this way, the inrush current may affect the voltagelevel of the input voltage source of the DC/DC converter. Thus, at thestart phase of the DC/DC converter, the error amplifier EA compares thefeedback voltage V_(FB) from the output voltage V_(OUT) with thesoft-start voltage V_(SOFT). In this way, the gain of the error signalS_(ERROR) generated by the error amplifier EA is not too high so as toreduce the inrush current of the DC/DC converter and therefore thevoltage level of the input voltage source of DC/DC converter at thestart phase of the DC/DC converter is not lowered.

Please refer to FIG. 2. FIG. 2 is a diagram illustrating therelationship between the soft-start voltage and the reference voltage.For the soft-start voltage having the characteristics described above,the soft-start voltage must be a voltage which rises gradually. When thesoft-start voltage V_(SOFT) is lower than the reference voltage V_(REF),which is so called the soft-start phase of the DC/DC converter, theerror amplifier EA compares the feedback voltage V_(FB) with thesoft-start voltage V_(SOFT) for generating the error signal S_(ERROR).When the soft-start voltage V_(SOFT) is higher than the referencevoltage V_(REF), which is so called the normal phase of the DC/DCconverter, the error amplifier EA compares the feedback voltage V_(FB)with the reference voltage V_(REF) for generating error signalS_(ERROR). For having a longer soft-start phase, the slope of thesoft-start voltage V_(SOFT) when the soft-start voltage V_(SOFT) risesmust be flatter. That is, the more gradually the soft-start voltageV_(SOFT) rises, the longer the start phase is, and the smaller the loadcurrent drained from the output voltage source V_(OUT) is. However, forrealizing the characteristic of the soft-start voltage V_(SOFT) to risegradually, generally it is achieved by a capacitor with relative largecapacitance or a charge current with relative small magnitude.

Please refer to FIG. 3. FIG. 3 is a diagram illustrating theconventional soft-start voltage circuit 300. As shown in FIG. 3, thesoft-start voltage circuit 300 comprises a capacitor C_(SOFT) and acurrent source I_(SOFT). The voltage over the capacitor C_(SOFT) isserved as the soft-start voltage V_(SOFT). As described in the previousparagraph, in the soft-start voltage circuit 300, it is required thatthe capacitance of the capacitor C_(SOFT) is large enough or the currentprovided by the current source I_(SOFT) is small enough for providing agradually rising soft-start voltage V_(SOFT) to prolong the start phase.However, the capacitor C_(SOFT) occupies a quite large area in a generalchip. Thus, utilizing the capacitor C_(SOFT) with the large capacitanceto realize the soft-start voltage circuit 300 wastes a substantial area.Moreover, when the current source I_(SOFT) provides a small enoughcurrent, the current source I_(SOFT) is easily affected by thefabrication so that the current provided by the current source I_(SOFT)is not as the same as expected. In other words, the period of thesoft-start phase is affected and not as expected. Therefore, regardlessof adjusting values of the capacitor C_(SOFT) or the current sourceI_(SOFT), it is quite inconvenient for the user.

SUMMARY OF THE INVENTION

The present invention provides a soft-start voltage circuit. Thesoft-start voltage circuit comprises an operational amplifier, a firstcapacitor, a voltage level shifter, a second capacitor, a first switch,and a second switch. The operational amplifier comprises a positiveinput end, a negative input end, and an output end, coupled to thenegative input end of the operational amplifier, for outputting asoft-start voltage. The voltage level shifter is coupled between thefirst capacitor and the positive input end of the operational amplifierfor shifting a voltage on the first capacitor with an offset voltage.The first switch is coupled between the first and the second capacitorsfor coupling the first and the second capacitors according to a clocksignal. The second switch is coupled between the second capacitor andthe negative input end of the operational amplifier for coupling thesecond capacitor and the negative input end of the operational amplifieraccording to an inverted signal corresponding to the clock signal.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an error amplifier in a DC/DCconverter.

FIG. 2 is a diagram illustrating the relationship between the soft-startvoltage and the reference voltage.

FIG. 3 is a diagram illustrating the conventional soft-start voltagecircuit.

FIG. 4 is a diagram illustrating the soft-start voltage circuit of thepresent invention.

FIG. 5 is a diagram illustrating the operation of the soft-start voltagecircuit.

FIG. 6 is a diagram further illustrating the operation of the soft-startvoltage circuit.

FIG. 7 is a timing diagram illustrating the relationship between theclock signal, the offset voltage, and the soft-start voltage.

DETAILED DESCRIPTION

Please refer to FIG. 4. FIG. 4 is a diagram illustrating the soft-startvoltage circuit 400 of the present invention. The soft-start voltagecircuit 400 is utilized during the soft-start phase of the DC/DCconverter for providing a gradually rising soft-start voltage V_(SOFT)to the error amplifier EA as shown in FIG. 1. The soft-start voltagecircuit 400 comprises an operational amplifier OP, a clock generator410, a voltage level shifter 420, an inverter INV₁, two switches SW₁ andSW₂, and two capacitors C₁ and C₂.

The clock generator 410 is utilized for generating a clock signal CLK.The inverter INV₁ is coupled to the clock generator 410 for invertingthe clock signal CLK and generating a clock signal CLKB accordingly.

The voltage level shifter 420 is coupled between the positive input endof the operational amplifier OP and the capacitor C₁ (the node B) forshifting the received voltage with an offset voltage V_(X) andoutputting the shifted voltage. More particularly, when the voltage onthe node B is V₁, the positive input end of the operational amplifier OPreceives a voltage with the magnitude (V₁+V_(X)), which is shifted bythe voltage level shifter 420.

The positive input end of the operational amplifier OP is coupled to thevoltage level shifter 420. The negative input end of the operationalamplifier OP (the node A) is coupled between the output end of theoperational amplifier OP and the second end 2 of the switch SW₂. Theoutput end of the operational amplifier OP is utilized to output thesoft-start voltage V_(SOFT).

The capacitor C₁ is coupled between voltage level shifter 420, the firstend 1 of the switch SW₁ (the node B), and the voltage source V_(SS)(ground end). The capacitor C₂ is coupled between the second end 2 ofthe switch SW₁, the first end 1 of the switch SW₂ (the node C), and thevoltage source V_(SS) (the ground end). In the following description,the capacitances of C₁ and C₂ are assumed equal for calculatingconveniently.

Both of the switches SW₁ and SW₂ comprise a first end 1, a second end 2,and a control end C. The first end of the switch SW₁ is coupled to thenode B. The second end of the switch SW₁ is coupled to the node C. Thecontrol end C of the switch SW₁ is coupled to the clock generator 410for receiving the clock signal CLK. The first end 1 of the switch SW₂ iscoupled to the node C. The second end 2 of the switch SW₂ is coupled tothe node A (the negative input end of the operational amplifier OP). Thecontrol end of the switch SW₂ is coupled to the inverter INV₁ forreceiving the clock signal CLKB (the inverted clock signal CLK). Whenthe control end C of the switch SW₁ receives the control signal withlogic “1”, the switch SW₁ is turned on, which means that the switch SW₁couples the first end 1 of the switch SW₁ to the second end 2 of theswitch SW₁. On the contrary, when the control end C of the switch SW₁receives the control signal with logic “0”, the switch SW₁ is turnedoff, which means that the switch SW₁ disconnects the first end 1 of theswitch SW₁ from the second end 2 of the switch SW₁. The operationprinciple of the switch SW₂ is the same as the switch SW₁, and therelated description is not repeated again. Furthermore, both of theswitches SW₁ and SW₂ can be realized with P channel Metal OxideSemiconductor (PMOS) transistors, and the control ends C of the switchesSW₁ and SW₂ are the gates of the PMOS transistors.

The operating principle of the soft-start voltage circuit 400 isdescribed in detail as below.

Please refer to FIG. 5. FIG. 5 is a diagram illustrating the operationof the soft-start voltage circuit 400. As shown in FIG. 5, when theclock generator 410 is turned on, the clock generator 410 firstgenerates a clock signal CLK with a low voltage level (logic “0”) forthe first half cycle, and a clock signal CLKB with a high voltage level(logic “1”) so that the switch SW₁ is turned off and the switch SW₂ isturned on. Meanwhile, assuming an initial voltage V_(INI) exists (pleasenote that the initial voltage V_(INI) can be 0 volt), the voltage V_(A)on the node A equals to (V_(INI)+V_(X)). That is, the soft-start voltageV_(SOFT) outputted from the operational amplifier OP equals to(V_(INI)+V_(X)) at the time.

Please refer to FIG. 6. FIG. 6 is a diagram further illustrating theoperation of the soft-start voltage circuit 400. As shown in FIG. 6,when the clock generator 410 is turned on for the first half cycle ofthe clock signal CLK, the clock generator 410 generates the clock signalCLK with a high voltage level (logic “1”) for the second half cycle, andthe clock signal CLKB with a low voltage level (logic “0”) for thesecond half cycle so that the switch SW₁ is turned on and the switch SW₂is turned off. Meanwhile, the former voltage V_(X) on the node A isshared by the capacitors C₁ and C₂ evenly. Thus, both of the voltageV_(B) on the node B and the voltage V_(C) on the node C are raised up to(V_(INI)+V_(X)/2). Consequently, the voltage of the positive input endof the operational amplifier OP is also raised up to(V_(INI)+V_(X)+V_(X)/2) and the voltage V_(A) on the node A is raised upto (V_(INI)+V_(X)+V_(X)/2) as well. That is, the soft-start voltageV_(SOFT) outputted from the soft-start circuit 400 is raised up to(V_(INI)+V_(X)+V_(X)/2), which is higher than the soft-start voltageV_(SOFT) during the first half cycle of the clock signal CLK by V_(X)/2.

From FIG. 5 and FIG. 6, it is known that by means of the operation ofthe clock generator 410 and the voltage level shifter 420, thesoft-start voltage V_(SOFT) is raised up with a voltage V_(X)/2 eachhalf cycle of the clock signal CLK so as to raise the soft-start voltageV_(SOFT) gradually. In addition, by controlling the frequency of theclock signal CLK generated from the clock generator 410 and the offsetvoltage V_(X) generated from the voltage level shifter 420, the slope ofthe soft-start voltage V_(SOFT) can be controlled effectively and theperiod of the soft-start phase can be precisely controlled as well.

Please refer to FIG. 7. FIG. 7 is a timing diagram illustrating therelationship between the clock signal CLK, the offset voltage V_(X), andthe soft-start voltage V_(SOFT). As shown in FIG. 7, every half cycle ofthe clock signal CLK, the soft-start voltage V_(SOFT) rises with avoltage V_(X)/2. That is, each cycle T passes, the soft-start voltageV_(SOFT) rises with an offset voltage V_(X). Thus, it can be seen inFIG. 7 that the slope of the soft-start voltage V_(SOFT) can be exactlycontrolled by the cycle of the clock signal CLK and the offset voltage,which allows users to exactly control the period of the soft-startphase.

In conclusion, the soft-start voltage circuit provided by the presentinvention can generate the soft-start voltage without the largecapacitor or the small current. Therefore, the area consumed in the chipcan be saved. Furthermore, in the present invention, the slope of thesoft-start voltage V_(SOFT) can be controlled by the clock signal andthe offset voltage. Thus, it provides a great convenience for the userto utilize the soft-start voltage circuit provided by the presentinvention for exactly controlling the period of the soft-start phase.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention.

1. A soft-start voltage circuit, comprising: an operational amplifier,comprising: a positive input end; a negative input end; and an outputend, coupled to the negative input end of the operational amplifier, foroutputting a soft-start voltage; a first capacitor; a voltage levelshifter, coupled between the first capacitor and the positive input endof the operational amplifier, for shifting a voltage on the firstcapacitor with an offset voltage; a second capacitor; a first switch,coupled between the first and the second capacitors, for coupling thefirst and the second capacitors according to a clock signal; and asecond switch, coupled between the second capacitor and the negativeinput end of the operational amplifier, for coupling the secondcapacitor and the negative input end of the operational amplifieraccording to an inverted signal corresponding to the clock signal. 2.The soft-start voltage circuit of claim 1, wherein the first switchcomprises: a first end, coupled to the first capacitor; a second end,coupled to the second capacitor; and a control end, for receiving theclock signal; wherein when the clock signal is at a low voltage level,the first end of the first switch is coupled to the second end of thefirst switch; wherein when the clock signal is at a high voltage level,the first end of the first switch is not coupled to the second end ofthe first switch.
 3. The soft-start voltage circuit of claim 2, whereinthe first switch is a P channel Metal Oxide Semiconductor (PMOS)transistor.
 4. The soft-start voltage circuit of claim 1, wherein thesecond switch comprises: a first end, coupled to the second capacitor; asecond end, coupled to the negative end of the operational amplifier;and a control end, for receiving the inverted signal corresponding tothe clock signal; wherein when the inverted signal corresponding to theclock signal is at a low voltage level, the first end of the secondswitch is coupled to the second end of the second switch; wherein whenthe inverted signal corresponding to the clock signal is at a highvoltage level, the first end of the second switch is not coupled to thesecond end of the second switch.
 5. The soft-start voltage circuit ofclaim 3, wherein the second switch is a PMOS transistor.
 6. Thesoft-start voltage circuit of claim 1, further comprising: a clockgenerator, coupled to the control end of the first switch, forgenerating the clock signal; and an inverter, coupled between the clockgenerator and the control end of the second switch, for generating theinverted signal corresponding to the clock signal.
 7. The soft-startvoltage circuit of claim 1, wherein the first capacitor and the secondcapacitor have the same capacitance.